Vertical power delivery cuts energy loss in AI processor designs
Next-generation power delivery architectures that route power vertically, placing regulators underneath processors rather than alongside them, can significantly reduce electrical losses, improve transient response and free up board space in high-performance AI hardware.
A EEWorld report explains how vertical power delivery (VPD) architectures are emerging as a response to the escalating power demands of modern AI processors (GPUs, ASICs and accelerators).
Traditional power-delivery networks (PDNs) route current laterally across circuit boards from external voltage regulators, which introduces resistance and inductance losses and generates excess heat, problems that worsen at the very high current levels typical of AI workloads.
In contrast, vertical power delivery relocates DC-DC converters and regulators beneath the processor, reducing the electrical path between the supply and load.
However, this reduces resistance and parasitic inductance, cutting I²R losses and improving transient response, critical for AI chips that experience rapid current shifts during computation. The cleaner power paths also help isolate high-speed signal traces from noise, enhancing signal integrity and electromagnetic compatibility.
Additional benefits include freed top-side board space for memory, optics and other components, which supports higher integration density without expanding board area. However, VPD introduces challenges such as thermal management and height constraints under the processor, requiring advanced packaging and heat-spreading solutions.
Emerging voltage-regulator technologies aim to match the speed of embedded regulators while avoiding their limitations in efficiency and die area consumption.
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